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document id# 080201 date: jun 18, 2002 rev: f version: 1 distribution: public document le79489 subscriber line interface circuit distinctive characteristics ideal for low power sensitive applications low standby power (normal and reverse) automatic on-chip battery switching on-chip thermal management on-chip thermal shutdown ?20 v to ?60 v battery operation programmable current limit programmable resistive feed programmable loop-detect threshold selectable overhead for metering applications two-wire impedance set by single external impedance on-chip ring and test relay drivers and relay snubber circuits polarity reversal (full transmission) loop and ground-key detector comparator for ring-trip detection ground-start capability on-hook transmission block diagram tw o - w i r e interface te s t r e l ay driver ring relay driver input decoder and control ring-trip comparator ground-key detector loop detector signal transmission power-feed controller switch control testout ringout c1 c2 c3 c4 e1 det rd vtx rsn rdc cas ovh rfa agnd/dgnd vcc bswth bswen bswout bgnd vbat1 vbat2 b(ring) hpb hpa a(tip) db da tmg
2 le79489 data sheet ordering information standard products legerity standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availability of specific valid combinations and to check on newly released combinations, and to obtain additional data on legerity?s standard military?grade products. *legerity reserves the right to fulfill all orders for this device with parts marked with the "am" part number prefix, until su ch time as all inventory bearing this mark has been depleted. it should be noted that parts marked with either the "am" or the "le" part number prefix are equivalent devices in terms of form, fit, and function. the only difference between the two is in the part number prefix appearing on the topside mark. valid combinations le79489* ?1 ?2 ?3 ?4 ?5 ?6 jc le79489* j c c = commercial (0 c to 70 c)* package type j = 32-pin plastic leaded chip carrier (pl 032) device number/description le79489 subscriber line interface circuit performance grade option ?1 = 52 db longitudinal balance, polarity reversal ?2 = 60 db longitudinal balance, polarity reversal ?3 = 52 db longitudinal balance, no polarity reversal ?4 = 60 db longitudinal balance, no polarity reversal ?5 = 52 db longitudinal balance, no polarity reversal, metering ?6 = 52 db longitudinal balance, polarity reversal, metering temperature range ?1
le79489 data sheet 3 connection diagram top view rd hpb nc rsn rsvd tmg testout vbat1 bswen c1 det e1 1 2 3 4 323130 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 da bswout vtx agnd/dgnd hpa c4 c3 c2 bswth cas ovh rfa rdc ringout vbat2 vcc bgnd b(ring) a(tip) db 32-pin plcc notes: 1. pin 1 is marked for orientation. 2. nc = no connect 3. rsvd = reserved. do not connect to this pin.
4 le79489 data sheet pin descriptions pin names type description agnd/dgnd gnd analog and digital ground. a(tip) output output of a(tip) power amplifier. bgnd gnd battery (power) ground. b(ring) output output of b(ring) power amplifier. bswen ? battery switch control. internally connected to automatic battery switch circuitry. bswen can be overridden by external logic. bswen low connects vbat1 to vbat2. bswen high disconnects vbat1 from vbat2. bswout output buffered output. internally connected to battery switch circuitry. the output is open- collector with a built-in pull-up resistor. bswout low indicates vbat1 is connected to vbat2. bswout high indicates vbat1 is disconnected from vbat2. this output is valid only in the active states. bswth input input for setting automatic battery switch threshold. normally tied to battery 2. tie to ground for manual switching. c3?c1 input decoder. ttl compatible. c3 is msb and c1 is lsb. c4 input test relay input ? active low. 1 = off. 0 = on. cas capacitor anti-sat pin for capacitor to filter reference voltage when operating in anti-sat region. da input ring-trip negative. negative input to ring-trip comparator. db input ring-trip positive. positive input to ring-trip comparator. det output switchhook detector. when enabled, a logic low indicates the selected detector is tripped. the detector is selected by the logic inputs (c3?c1). the output is open-collector with a built-in 15 k ? pull-up resistor. e1 input ground-key detect select. e1 = 1 selects the hook switch detector. e1 = 0 selects the ground-key detector. in the tip open state, ground key is selected independent of e1. hpa capacitor high-pass filter capacitor. a(tip) side of high-pass filter capacitor. hpb capacitor high-pass filter capacitor. b(ring) side of high-pass filter capacitor. nc ? no connect. this pin not internally connected. ovh input overhead control. logic high enables minimized nonmetering overhead. logic low enables 2.2 v metering dc overhead. ttl-compatible. rd resistor detector resistor. detector threshold set and filter pin. rdc resistor dc feed resistor. connection point for the dc feed current programming network. the other end of the network connects to the receiver summing node (rsn). connection point for the dc feed current programming network. the other end of the network connects to rsn. v rdc is negative for normal polarity and positive for reverse polarity. rfa ? resistive feed adjust. adjust the dc feed resistance gain coefficient, gdc, with external resistor connected to ground. ringout output ring relay driver. open-collector driver with emitter internally connected to bgnd. rsn input receive summing node. the metallic current (ac and dc) between a(tip) and b(ring) is equal to 500 times the current into this pin. the networks that program receive gain, two-wire impedance, and feed current all connect to this node. rsvd ? reserved. these pins are reserved for legerity use. make no connection to these pins. testout output test relay driver. open collector driver with emitter internally connected to agnd. tmg ? thermal management. external resistor connects this pin to vbat2 to offload power dis- sipation from slic. functions during normal polarity, active state. vbat1 battery most negative battery supply and substrate connection. vbat2 battery battery supply for output power amplifiers. switched to vbat1 by bswen. vcc power +5 v power supply. vtx output transmit audio. this output is a 0.5066 unity gain version of the a(tip) and b(ring) metallic voltage. vtx also sources the two-wire input impedance programming network.
le79489 data sheet 5 absolute maximum ratings storage temperature . . . . . . . . . . . . ?55c to +150c with respect to agnd/dgnd: v cc . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.4 v to +7.0 v v bat1 continuous . . . . . . . . . . . . . . . . . . +0.4 v to ?70 v 10 ms . . . . . . . . . . . . . . . . . . . . . . +0.4 v to ?75 v v bat2 and bswth. . . . . . . . . . . . . . . +0.4 v to v bat1 bgnd. . . . . . . . . . . . . . . . . . . . . . . . . . . .+3 v to ?3 v a(tip) or b(ring) with respect to bgnd: continuous . . . . . . . . . . . . . . . . . . . . v bat1 to +1 v 10 ms (f = 0.1 hz) . . . . . . . . . . . . . . . ?70 v to +5 v 1 s (f = 0.1 hz) . . . . . . . . . . . . . . . . ?80 v to +8 v 250 ns (f = 0.1 hz) . . . . . . . . . . . . . ?90 v to +12 v current from a(tip) or b(ring). . . . . . . . . . 150 ma testout/ringout/current. . . . . . . . . . . . . . 80 ma testout/ringout/voltage . . . . . . . bgnd to +7 v testout/ringout/transient . . . . . bgnd to +10 v da and db inputs voltage on ring-trip inputs . . . . . . . . . . v bat1 to 0 v current on ring-trip inputs . . . . . . . . . . . . . 10 ma c4?c1, bswen, ovh, e1 input voltage . . . . . . . . . . . . ?0.4 v to v cc + 0.4 v maximum power dissipation, continuous t a = 70c, no heat sink (see note): in 32-pin plcc package. . . . . . . . . . . . . . . . 1.7 w thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . ja in 32-pin plcc package. . . . . . . . . . . .43c/w typ esd immunity/pin (hbm) . . . . . . . . . . . . . . . . . 1500 v note: thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165 c. the device should never be exposed to this temperature. operation above 145 c junction temperature may degrade device reliability. see the slic packaging considerations section for more information. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature. . . . . . . . . . . . . ?40c to +85c* v cc . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 v to 5.25 v bat1 . . . . . . . . . . . . . . . . . . . . . . . . . ?40.5 v to ?60 v bat2 . . . . . . . . . . . . . . . . . . . . . . . . . . .?20 v to bat1 agnd/dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v bgnd with respect to gnd . . . ?100 mv to +100 mv load resistance on vtx to gnd. . . . . . . . . 20 k ? min operating ranges define those limits over which the functionality of the device is guaranteed by production testing. * legerity guarantees the performance of this device over commercial (0 to 70 c) and industrial (-40 to 85 c) temperature ranges by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to periodic sampling. these characterization and test procedures comply with section 4.6.2 of bellcore tr-tsy-000357 component reliability assurance requirements for telecommunications equipment.
6 le79489 data sheet electrical characteristics description test conditions (see note 1) min typ max unit note transmission performance 2-wire return loss (see test circuit d) 200 hz to 3.4 khz 26 db 4, 6 analog output (v tx ) impedance 3 20 ? 4 analog output (v tx ) offset voltage ?50 +50 mv overload level, 2-wire active state 2.5 vpk 2a, 3 active state, ovh = 0 ?5, ?6* 7 overload level open loop, r lac = 900 ? ,?5, ?6* ovh = 0 3.86 vrms 2b, 3 thd, total harmonic distortion 0 dbm ?64 ?50 db 3 +7 dbm ?55 ?40 thd, open loop 0 dbm, r lac = 600 ? ?36 4 longitudinal capability (see test circuit c) longitudinal to metallic l-t 200 hz to 1 khz normal and reverse polarity ?1, ?6* normal polarity ?3, ?5 normal polarity 0c to +70c ?2, ?4 normal polarity ?40c to +85c ?2, ?4 reverse polarity ?40c to +85c ?2 52 52 60 58 54 db 8 longitudinal to metallic l-t 1 khz to 3.4 khz normal and reverse polarity ?1, ?6* normal polarity ?3, ?5 normal polarity 0 c to +70c ?2, ?4 normal polarity ?40c to +85c ?2, ?4 reverse polarity ?40c to +85c ?2 52 52 54 54 54 longitudinal signal generation 4-l 200 hz to 3.4 khz 40 db longitudinal current per pin (a or b) active state 15 27 marms 7 longitudinal impedance at a or b 0 to 100 hz 25 ? /pin 4 longitudinal induction 23 dbrnc 4 idle channel noise c-message weighted noise r l = 600 ? +7 +12 dbrnc 4, 8 psophometric weighted noise r l = 600 ? ?83 ?78 dbmp 8 insertion loss (see test circuits a and b) gain, 4- to 2-wire 0 dbm, 1 khz 0c to 70c ?40c to 85c ?0.15 0 +0.15 db ?0.20 0 +0.20 4 gain, 2- to 4-wire, 4-to-4-wire 0 dbm, 1 khz 0c to 70c ?40c to 85c ?6.05 ?5.90 ?5.75 ?6.10 ?5.90 ?5.70 4 gain, 4- to 2-wire open loop ?0.35 +0.35 4 gain, 2- to 4-wire, 4- to 4-wire open loop ?6.25 ?5.90 ?5.55 4 gain over frequency 300 to 3.4 khz, relative to 1 khz ?0.10 +0.10 gain tracking +3 dbm to ?55 dbm relative to 0 dbm ?0.10 +0.10 gain tracking open loop 0 db to ?15 db ?0.35 +0.35 4 group delay 0 dbm, 1 khz 4 s 4, 6 note: * p.g. = performance grade
le79489 data sheet 7 line characteristics i l , active short loop medium loop long loop r ldc = 250 ? r ldc = 700 ? r ldc = 2 k ? 44.2 33.4 17.2 48.6 37.1 19.2 54.0 40.8 21.2 ma i l , active short loop ovh = 0 medium loop long loop r ldc = 250 ? r ldc = 700 ? ?5, ?6* r ldc = 2 k ? 44.2 33.4 16.0 48.6 37.1 18.0 54.0 40.8 20.0 i l , accuracy, standby state t a = 25 c 0.7 i l i l 1.3 i l current limited region 18 30 i l , loop current, disconnect state r l = 0 100 a i l lim active, a and b to gnd 95 135 ma v apparent 52 v 4 v ab , open loop voltage active, normal reverse polarity ovh = 0 40.3 39.8 37 41.7 41.7 39 bat sw hysteresis 1150 mv bat sw threshold bat2 + 8.5 v (from v bat1 to v bat2 ) ovh = 0 ?5, ?6* bat2 + 11.7 i a , leakage, tip open state r l = 0 100 a i b , current, tip open state b to gnd 18 30 56 ma v a , active ra to bat1 = 7 k ? , rb to gnd = 100 ? ?7.5 ?5 v 4 power supply rejection ratio (vripple = 100 mvrms), active normal state v cc 50 hz to 3.4 khz 30 45 db 3 v bat1 50 hz to 3.4 khz 28 50 v bat2 50 hz to 3.4 khz 35 50 4 v bat1 , open loop, r lac = 600 ? (anti-sat region) 50 hz 100 hz 200 hz 500 hz to 3.4 khz 8 15 20 28 14 22 29 40 4 effective internal resistance cas pin to gnd 85 170 255 k ? 4 device power dissipation open loop, disconnect state 35 70 mw open loop, standby state 50 85 open loop, active state ovh = 1 150 250 open loop, active state ovh = 0 550 620 9 off hook, standby state r l = 600 ? 1000 1300 off hook, active state r l = 250 ? r l = 700 ? 880 800 1200 1000 electrical characteristics (continued) description test conditions (see note 1) min typ max unit note i l v bat1 3 v ? r l 400 + ---------------------------------- - =
8 le79489 data sheet supply currents, battery i cc , open loop v cc supply current disconnect state standby state active state 2.5 3.0 6.3 4.5 4.5 9.5 ma i bat1 , open loop v bat1 supply current disconnect state standby state active state 0.5 0.7 2.8 1.0 1.5 4.8 rfi rejection rfi rejection 100 khz to 30 mhz (see figure e) 0.7 mvrms 4 logic inputs (c4?c1, e1, bswen, ovh [?5, ?6 only]) v ih , input high voltage c3 c1, c2, c4, bswen, ovh, e1 2.5 2.0 v v il , input low voltage 0.8 i ih , input high current c4?c1, ovh, e1 ?75 40 a i ih , input high current, bswen ?75 1200 i il , input low current, except c1 ?400 i il , input low current, c1 ?600 ?300 logic output (det , bswout) v ol , output low voltage i out = 0.3 ma 0.40 v v oh , output high voltage i out = ?0.05 ma 2.4 ring-trip comparator input (da, db) bias current ?500 ?50 na offset voltage source resistance = 2 m ? ?50 0 +50 mv 5 loop detector i t , loop-detect threshold tolerance active state, off-hook to on-hook r d = 35.4 k ? , i t = 368/r d on-hook to off-hook r d = 35.4 k ? , i t = 414/r d ?15 ?20 +15 +20 % standby state, off-hook to on-hook r d = 35.4 k ? , i t = 425/r d on-hook to off-hook r d = 35.4 k ? , i t = 471/r d ?15 ?20 +15 +20 loop-detect threshold hysteresis active state 1.3 ma 4 standby state igk, gnd key-detector threshold r l from bx to gnd active, standby, and tip open states 5913 relay driver output (ringout/testout) on voltage i ol = 40 ma +0.3 +0.7 v off leakage v oh = +5 v 100 a zener breakover i z = 100 a 6 7.5 v zener on voltage i z = 40 ma 7.9 10 electrical characteristics (continued) description test conditions (see note 1) min typ max unit note
le79489 data sheet 9 relay driver schematics notes: 1. unless otherwise specified, test conditions are v cc = +5 v, bat1 = ?50 v, bat2 = ?34 v, r l = 600 ? , r dc1 = r dc2 = 5.833 k ? , r tmg = 570 ? , r d = 35.4 k ? , rfa = 0 ? , no fuse resistors, c hp = 0.22 f, c dc = 0.5 f, c cas = 0.33 f, c vbat12 = 220 nf, d 1 =d 2 = 1n400x, ovh = 1, two-wire ac input impedance is a 600 ? resistance synthesized by the programming network shown below. 2. a. overload level exists when thd = 1%. b. overload level exists when thd = 1.5%. 3. this parameter is tested at 1 khz in production. performance at other frequencies is guaranteed by characterization. 4. not tested in production. this parameter is guaranteed by characterization or correlation to other tests. 5. tested with 0 ? source impedance. 2 m ? is specified for system design only. 6. group delay can be greatly reduced by using a z t network such as that shown in note 1 above. the network reduces the group delay to less than 2 s and increases 2wrl. the effect of group delay on linecard performance also may be compensated for by synthesizing complex impedance with the dslac? or qslac? device. 7. minimum current level is guaranteed not to cause a false loop detect. the slic must be functional in this condition. 8. four-wire performance is 5?9 db better than the specified two-wire values. 9. open loop, active state, metering mode power dissipation may be reduced from a typical of 550 mw to a typical of 150 mw by connecting the det pin to the ovh pin. this connection will force the slic into the nonmetering mode while on hook. with this connection, a metering signal sent after the slic goes on hook may be distorted on the 2w line because the slic is forced into the nonmetering mode. to eliminate this distortion, a delay can be added between the time the slic goes on hook and the time the slic switches to nonmetering mode by using an rc circuit for the det pin to ovh pin connection. bgnd testout bgnd ringout c t1 = 120 pf vtx rsn v rx r rx = 150 k ? r t1 = 76 k ? r t2 = 76 k ?
10 le79489 data sheet table 1. slic decoding det output state c3 c2 c1 2-wire status e1 = 1 e1 = 0 0 0 0 0 standby, reverse polarity loop detector gk 1 0 0 1 reserved x x 2 0 1 0 active, reverse polarity loop detector gk 3 0 1 1 tip open gk or loop detector gk 4 1 0 0 disconnect ring trip ring trip 5 1 0 1 ringing ring trip ring trip 6 1 1 0 active, normal loop detector gk 7 1 1 1 standby, normal loop detector gk table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired two-wire ac input impedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. the internal amplifier pole is: z rx is connected from vrx to rsn. z t is defined above, and g 42l is the desired receive gain. z l is the 2-wire load impedance. r dc1 , r dc2 , and c dc form the network connected to the r dc pin. r dc1 and r dc2 are approximately equal. i limit is the desired loop current in the constant-current region. r d and c d form the network connected from r d to agnd/ dgnd and i t is the threshold current between on hook and off hook in the active state. c cas is the regulator filter capacitor and f c is the desired filter cutoff frequency. standby loop current (resistive region). z t 253 z 2win 2r f ? () = 22 khz r lac ? 600 ? 10% -------------------------------------- z rx z l g 42l ----------- - 500 z t () z t 253 z l 2r f + () + --------------------------------------------------- ? = i limit 625 gfa () r dc1 r dc2 + --------------------------------- = c dc 1.5 ms r dc1 r dc2 + r dc1 r dc2 ? ------------------------------- - ? = gfa 0.99 rfa 30.1 k ? + () rfa 32 k ? + () ------------------------------------------ - ? = rcl 1.4 r dc1 r dc2 + () ? rfa 60 k ? + () rfa 100 k ? + () ----------------------------------------- ? = r d 365 i t -------- - , = c d 0.5 ms r d --------------- - = c cas 1 3.4 10 5 f c ? ----------------------------- - = i sdby tan v bat1 3 v ? 400 ? r l + ---------------------------------- - =
le79489 data sheet 11 c bswen is connected from bswen to gnd for automatic switching. t d is the delay in switching from bat1 to bat2. the delay from bat2 to bat1 is about 0.1 t d . the dc feed resistance can be adjusted with a resistance (rfa) from the rfa pin to ground. thermal management equations (active, normal, and reverse polarity states) (ovh = 1) (ovh = 0) r tmg is connected from tmg to vbat2 and is used to limit power dissipation within the slic in active states only. (ovh = 1) (ovh = 0) power dissipated in the thermal management resistor, r tmg , during the active states. power dissipated in the slic while in the active states. table 2. user-programmable components (continued) c bswen 5 mhos t d ms () ? = r feed 2r fuse r dc1 r dc2 + gdc --------------------------------- ?? ?? + ? = gdc 47.9 40 k ? rfa + 120 k ? rfa + ------------------------------------ ?? ?? = r tmg v bat2 6 v ? i loopmax ---------------------------------- - r tmg v bat2 7.5 v ? i loopmax --------------------------------------- p rtmg v bat2 6 v ? i l r l ? () ? () 2 r tmg () r tmg 40 + () 2 ------------------------------------------------------------------------------------------- - = p rtmg v bat2 7.5 v ? i l r l ? () ? () 2 r tmg () r tmg 40 + () 2 ------------------------------------------------------------------------------------------------ - = p slic v bat2 ( i l ) p rtmg ? r l ? i l () 2 ? ? 0.22 w + =
12 le79489 data sheet dc feed characteristics r dc = r dc1 + r dc2 = 11.67 k ?, rfa = 0 ? no fuse resistors ovh = 1 bat1 = ?50 v a. load line (typical) notes: graph is for illustration only. 1. 2. 3a. 3b. v ab i limit rcl i l ? ? rcl ? = v ab 52 v i l rdc gdc ------------ - ?? ?? ? = v ab 0.8 v bat1 2.2 i l rdc 5gdc ? ------------------------ - ?? ?? , ovh = 1 ? + = v ab 0.8 v bat1 2.2 i l rdc 5gdc ? ------------------------ - ?? ?? , ovh = 1 ? + = v ab 0.8 v bat1 1.0 ? i l rdc 5 gdc ? ------------------------ ?? ?? , ovh = 0 ? = figure 1. dc feed characteristics b. feed programming a b i l rsn rdc r dc1 r dc2 c dc slic r l a b 60 0 0 41.5 v 2 3 60 i l (ma) 18.8 ma, 38.8 v 1 50.0 ma 48.0 ma, 18.5 v v ab ( volts ) feed current programmed by r dc1 and r dc2
le79489 data sheet 13 test circuits i l2-4 = ?20 log (v tx / v ab ) a. two- to four-wire insertion loss v ab r l 2 r l 2 a(tip) b(ring) vtx rsn agnd slic v ab a(tip) b(ring) vtx rsn agnd slic r l i l4-2 =?20log (v ab / v rx ) b. four- to two-wire insertion loss r t r t r rx r rx v rx v l v ab a(tip) b(ring) vtx rsn agnd slic v l s2 open, s1 closed l-t long. bal. = 20 log (v ab / v l ) l-4 long. bal. = 20 log (v tx / v l ) c. longitudinal balance r t r rx v rx s2 r l 2 r l 2 s1 v l c 1 c << r l s2 closed, s1 open 4-l long. sig. gen. = 20 log (v l / v rx )
14 le79489 data sheet test circuits (continued) d. two-wire return loss test circuit a(tip) b(ring) vtx rsn agnd slic z d is the specified nominal input impedance. r t1 r rx e. rfi test circuit r t2 r r v s v m z in c t1 hf gen vtx b a cax 33 nf cbx 33 nf c 1 c 2 rf 1 rf 2 50 ? 50 ? 200 ? 200 ? l 1 l 2 50 ? 1.5 vrms 80% amplitude modulated 100 khz to 30 mhz slic under test z d return loss = ?20 log (2 v m / v s )
le79489 data sheet 15 test circuits (continued) hpa vtx a(tip) v rx b(ring) vcc tmg testout cas rd ringout f. le79489 test circuit da db +5 v rsn r d r t r rx v tx rdc r dc2 c dc r dc1 agnd/ dgnd rfa rfa bswout ovh bswen c4 c3 c2 c1 e1 det c cas vbat1 bswth vbat2 bat1 bat2 a(tip) 2.2 nf hpb bgnd b(ring) d 1 r tmg 2.2 nf c hp battery ground analog ground digital ground c vbat12 (optional) (optional) c d
16 le79489 data sheet physical dimensions 32-pin plcc
17 le79489 data sheet revision summary revision c to revision d ? in the electrical characteristics table on page 8, some information was changed in the test conditions column in the loop detector section and the ?loop-detect threshold hysteresis? row was added to this section. revision d to revision e ? the physical dimensions (pl032) were added to the physical dimensions section. ? updated the pin description table to correct inconsistencies. revision e to revision f ? updated opn (ordering part number) throughout document. ? absolute maximum ratings: notes updated to standard. ? operating ranges: temperature statement updated to standard. ? updated "sales office listing." ? updated physical dimension drawings.
the contents of this document are provided in connection with legerity, inc. products. legerity makes no representations or war ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time with out notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. except as set forth in legerity's standard te rms and conditions of sale, legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. legerity reserves the right to discontinue or make changes to its products at any time without notice. ? 2002 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof, and qslac, dslac, are trademarks of legerity, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies.
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